EPF6010ATC144-1

Product Summary

The EPF6010ATC144-1 is a programmable logic device (PLD). It provides a low-cost alternative to high-volume gate array designs. The EPF6010ATC144-1 is based on the OptiFLEX architecture, which minimizes die size while maintaining high performance and routability. The EPF6010ATC144-1 has reconfigurable SRAM elements, which give designers the flexibility to quickly change their designs during prototyping and design testing. Designers can also change functionality during operation via in-circuit reconfiguration.

Parametrics

EPF6010ATC144-1 absolute maximum ratings: (1)VCC, Supply voltage With respect to ground: –2.0 to 7.0 V; (2)VI, DC input voltage: –2.0 to 7.0 V; (3)IOUT, DC output current, per pin: –25 to 25 mA; (4)TSTG, Storage temperature No bias: –65 to 150℃; (5)TAMB, Ambient temperature Under bias: –65 to 135℃; (6)TJ, Junction temperature: 135℃.

Features

EPF6010ATC144-1 features: (1)Provides an ideal low-cost, programmable alternative to high-volume gate array applications and allows fast design changes during prototyping or design testing; (2)Register-rich, look-up table- (LUT-) based architecture; (3)OptiFLEX architecture that increases device area efficiency; (4)Typical gates ranging from 5,000 to 24,000 gates; (5)Built-in low-skew clock distribution tree; (6)100% functional testing of all devices; test vectors or scan chains are not required; (7)In-circuit reconfigurability (ICR) via external configuration device or intelligent controller; (8)5.0-V devices are fully compliant with peripheral component interconnect Special Interest Group (PCI SIG) PCI Local Bus Specification; (9)Built-in Joint Test Action Group (JTAG) boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990, available without consuming additional device logic; (10)MultiVolt TM I/O interface operation, allowing a device to bridge between systems operating at different voltages; (11)Low power consumption (typical specification less than 0.5 mA in standby mode) ; (12)3.3-V devices support hot-socketing.

Diagrams