Product Summary

The K4D551638H-LC40D is a 268,435,456 bits of hyper synchronous data rate Dynamic RAM organized as 4 x 4,194,304 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 1.4GB/s/chip. I/O transactions are possible on both edges of the clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the K4D551638H-LC40 to be useful for a variety of high performance memory system applications.

Parametrics

K4D551638H-LC40 absolute maximum ratings: (1)Voltage on any pin relative to Vss VIN, VOUT: -0.5 to 3.6V; (2)Voltage on VDD supply relative to Vss VDD: -1.0 to 3.6V; (3)Voltage on VDD supply relative to Vss VDDQ: -0.5 to 3.6V; (4)Storage temperature TSTG: -55 to +150℃; (5)Power dissipation PD: 2.0W; (6)Short circuit current IOS: 50mA.

Features

K4D551638H-LC40 features: (1)2.6V + 0.1V power supply for device operation; (2)2.6V + 0.1V power supply for I/O interface; (3)SSTL_2 compatible inputs/outputs; (4)4 banks operation; (5)MRS cycle with address key programs; (6)All inputs except data & DM are sampled at the positive going edge of the system clock; (7)Differential clock input; (8)No Wrtie-Interrupted by Read Function; (9)Data I/O transactions on both edges of Data strobe; (10)DLL aligns DQ and DQS transitions with Clock transition; (11)Edge aligned data & data strobe output; (12)Center aligned data & data strobe input; (13)DM for write masking only; (14)Auto & Self refresh; (15)32ms refresh period (4K cycle) for -TC2A/33/36/40/45; (16)64ms refresh period (8K cycle) for -TC50/60; (17)66pin TSOP-II; (18)Maximum clock frequency up to 350MHz; (19)Maximum data rate up to 700Mbps/pin.

Diagrams

K4D551638H-LC40 block diagram