XC56L307VF160

Product Summary

The XC56L307VF160 is a 24-Bit Digital Signal Processor. The device supports network applications with general filtering operations. The XC56L307VF160 executes filter algorithms in parallel with core operations, enhancing signal quality with no impact on channel throughput or total channels supported. The result is increased overall performance. The XC56L307VF160 performs at 160 million multiply-accumulates per second (MMACS), attaining 320 MMACS when the EFCOP is in use. It operates with an internal 160 MHz clock with a 1.8 volt core and independent 3.3 volt input/output (I/O) power. The applications of the XC56L307VF160 include Wireless and wireline infrastructure applications, Multi-channel wireless local loop systems, DSP resource boards, High-speed modem banks and Packet telephony.

Parametrics

XC56L307VF160 absolute maximum ratings: (1)Supply Voltage, VCC: –0.1 to 2.0 V; (2)Input/Output Supply Voltage, VCCQH: –0.3 to 4.0 V; (3)All input voltages, VIN: GND – 0.3 to VCCQH + 0.3 V; (4)Current drain per pin excluding VCC and GND, I: 10 mA; (5)Operating temperature range, TJ: –40 to +100℃; (6)Storage temperature, TSTG: –55 to +150℃.

Features

XC56L307VF160 features: (1)160 million multiply-accumulates per second (MMACS) (321 MMACS using the EFCOP in filtering applications) with a 160 MHz clock at 1.8 V core and 3.3 V I/O; (2)Object code compatible with the DSP56000 core with highly parallel instruction set; (3)Data arithmetic logic unit (Data ALU) with fully pipelined 24-bit parallel multiplier-accumulator (MAC), 56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional ALU instructions, and 24-bit or 16-bit arithmetic support under software control; (4)Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for DSP applications (including immediate offsets), internal instruction cache controller, internal memoryexpandable hardware stack, nested hardware DO loops, and fast auto-return interrupts.

Diagrams