Product Summary

The EP1C6T144I7N is an field programmable gate array. It is based on a 1.5-V, 0.13-μm, all-layer copper SRAM process, with densities up to 20,060 logic elements (LEs) and up to 288 Kbits of RAM. With features like phaselocked loops (PLLs) for clocking and a dedicated double data rate (DDR) interface to meet DDR SDRAM and fast cycle RAM (FCRAM) memory requirements, the EP1C6T144I7N is a cost-effective solution for data-path applications. The EP1C6T144I7N supports various I/O standards, including LVDS at data rates up to 311 megabits per second (Mbps) and 66-MHz, 32-bit peripheral component interconnect (PCI), for interfacing with and supporting ASSP and ASIC devices.

Parametrics

EP1C6T144I7N absolute maximum ratings: (1)VCCINT Supply voltage: –0.5 to 2.4 V; (2)VCCIO: –0.5 to 4.6 V; (3)VI DC input voltage: –0.5 to 4.6 V; (4)IOUT DC output current, per pin: –25 to 25 mA; (5)TSTG Storage temperature: –65 to 150 ℃; (6)TAMB Ambient temperature: –65 to 135 ℃; (7)TJ Junction temperature: 135 ℃.

Features

EP1C6T144I7N features: (1)2,910 to 20,060 LEs; (2)Up to 294,912 RAM bits (36,864 bytes); (3)Supports configuration through low-cost serial configuration device; (4)Support for LVTTL, LVCMOS, SSTL-2, and SSTL-3 I/O standards; (5)Support for 66-MHz, 32-bit PCI standard; (6)Low speed (311 Mbps) LVDS I/O support; (7)Up to two PLLs per device provide clock multiplication and phase shifting; (8)Up to eight global clock lines with six clock resources available per logic array block (LAB) row; (9)Support for external memory, including DDR SDRAM (133MHz), FCRAM, and single data rate (SDR) SDRAM; (10)Support for multiple intellectual property (IP) cores, including Altera. MegaCore. functions and Altera Megafunctions Partners Program (AMPPSM) megafunctions.

Diagrams

EP1C6T144I7N diagram

Image Part No Mfg Description Data Sheet Download Pricing
(USD)
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EP1C6T144I7N
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