(China (Mainland))
Product Summary
The HY5DU561622FTP-4-C is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM. It is ideally suited for the point-to-point applications which requires high bandwidth. The HY5DU561622FTP-4-C offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
Parametrics
HY5DU561622FTP-4-C absolute maximum ratings: (1)Ambient Temperature:0 to 70℃; (2)Storage Temperature:-55 to 125℃; (3)Voltage on Any Pin relative to VSS:-0.5 to 3.6 V; (4)Voltage on VDD relative to VSS:-0.5 to 3.6 V; (5)Voltage on VDDQ relative to VSS:-0.5 to 3.6 V; (6)Output Short Circuit Current:50 mA; (7)Power Dissipation:1W.
Features
HY5DU561622FTP-4-C features: (1)All inputs and outputs are compatible with SSTL_2 interface; (2)JEDEC standard 400mil 66pin TSOP-II with 0.65mm pin pitch; (3)Fully differential clock inputs (CK, /CK) operation; (4)Double data rate interface; (5)Source synchronous - data transaction aligned to bidirectional data strobe (DQS); (6)x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O; (7)Data outputs on DQS edges when read (edged DQ) ; (8)Data inputs on DQS centers when write (centered DQ); (9)Data(DQ) and Write masks(DM) latched on the both rising and falling edges of the data strobe; (10)Write mask byte controls by LDM and UDM; (11)Programmable /CAS latency 3 / 4 supported; (12)Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode; (13)Internal 4 bank operations with single pulsed /RAS; (14)tRAS Lock-Out function supported; (15)Auto refresh and self refresh supported; (16)8192 refresh cycles / 64ms; (17)Full, Half and Matched Impedance(Weak) strength ; (18)driver option controlled by EMRS.
Diagrams
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HY5DS283222BF |
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HY5DU121622A |
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