(China (Mainland))
Product Summary
The K4H560838H-UCB3 is a 268,435,456 bits of double data rate synchronous DRAM organized as 4x 8,388,608 words by 4/8/16bits. The K4H560838H-UCB3 is fabricated with SAMSUNG’s high performance CMOS technology. Synchronous features with Data Strobe allow extremely high performance up to 400Mb/s per pin. I/O transactions are possible on both edges of DQS. Range of operating frequencies, programmable burst length and programmable latencies allow the device to be useful for a variety of high performance memory system applications.
Parametrics
K4H560838H-UCB3 absolute maximum ratings: (1)Voltage on any pin relative to VSS:-0.5 to 3.6 V; (2)Voltage on VDD & VDDQ supply relative to VSS:-1.0 to 3.6 V; (3)Storage temperature:-55 to +150℃; (4)Power dissipation:1.5 W; (5)Short circuit current:50 mA.
Features
K4H560838H-UCB3 features: (1)All inputs except data & DM are sampled at the positive going edge of the system clock(CK); (2)Data I/O transactions on both edges of data strobe ; (3)Edge aligned data output, center aligned data input; (4)LDM,UDM for write masking only (x16); (5)DM for write masking only (x4, x8); (6)Auto & Self refresh; (7)7.8us refresh interval(8K/64ms refresh) ; (8)Maximum burst refresh cycle : 8; (9)66pin TSOP II Pb-Free package; (10)Double-data-rate architecture; two data transfers per clock cycle; (11)Bidirectional data strobe [DQS] (x4,x8) & [L(U)DQS] (x16) ; (12)Four banks operation; (13)Differential clock inputs(CK and CK); (14)DLL aligns DQ and DQS transition with CK transition.
Diagrams
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 K4H510438B-G(Z)C/LA2 |
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K4H510438B-G(Z)C/LB0 |
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K4H510438B-G(Z)C/LB3 |
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Negotiable |
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K4H510438B-G(Z)C/LCC |
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Negotiable |
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K4H510438C-UCA2 |
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Negotiable |
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K4H510638E-LA2 |
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Negotiable |
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