(China (Mainland))
Product Summary
The MT48LC16M16A2P-75:D is a high-speed CMOS, dynamic random-access memory containing 268,435,456 bits. It is internally configured as a quad-bank DRAM with a synchronous interface (all signals are registered on the positive edge of the clock signal, CLK). The MT48LC16M16A2P-75:D is organized as 8192 rows by 2048 columns by 4bits.
Parametrics
MT48LC16M16A2P-75:D absolute maximum ratings: (1)Voltage on VDD/VDDQ supply relative to VSS VDD/VDDQ: –1 to +4.6 V; (2)Voltage on inputs, NC, or I/O balls relative to VSS VIN: –1 to +4.6V; (3)Storage temperature (plastic) TSTG: –55 +150℃; (4)Power dissipation: 1 W.
Features
MT48LC16M16A2P-75:D features: (1)PC100- and PC133-compliant; (2)Fully synchronous; all signals registered on positive edge of system clock; (3)Internal, pipelined operation; column address can be changed every clock cycle; (4)Internal banks for hiding row access/precharge; (5)Programmable burst lengths: 1, 2, 4, 8, or full page; (6)Auto precharge, includes concurrent auto pre-charge and auto refresh modes; (7)Self refresh mode (not available on AT devices); (8)Auto refresh: 64ms, 8192-cycle (commercial and industrial); 16ms, 8192-cycle (automotive); (9)LVTTL-compatible inputs and outputs; (10)Single +3.3V ±0.3V power supply.
Diagrams
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 MT48LC16M16A2P-75:D |
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IC SDRAM 256MBIT 133MHZ 54TSOPII |
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MT48LC16M16A2P-75:D TR |
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IC SDRAM 256MBIT 133MHZ 54TSOP |
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