XC2C64A-5CPG56C

CPLD, 56-CSBGA, 263MHz, 1.8V, XC2C64A-5CPG56C

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PartNumber:: XC2C64A-5CPG56C

Brand:: Xilinx, Inc - Xilinx | Pack: BGA | D/C: 10+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

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Products Upload time: 2012-06-01

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Part Number:XC2C64A-5CPG56C
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Product Summary

The XC2C64A-5CPG56C is a CPLD. It delivers the high speed and ease of use associated with the XC9500/XL/XV CPLD family with the extremely low power versatility of the XPLA3 family in a single CPLD. This means that the exact same parts of the XC2C64A-5CPG56C can be used for high-speed data communications/computing systems and leading edge portable products, with the added benefit of In System Programming. Low power consumption and high-speed operation are combined into the XC2C64A-5CPG56C that is easy to use and cost effective.

Parametrics

XC2C64A-5CPG56C absolute maximum ratings: (1)VCC, Supply voltage relative to GND: –0.5 to 2.0 V; (2)VI, Input voltage relative to GND: –0.5 to 4.0 V; (3)TA, Ambient Temperature (C-grade): 0 to 70℃; Ambient Temperature (I-grade): –40 to 85℃; (4)TJ, Maximum junction temperature: –40 to 150℃; (5)TSTR, Storage temperature: –65 to 150℃.

Features

XC2C64A-5CPG56C features: (1)Optimized for 1.8V systems: Industry fastest low power CPLD; Densities from 32 to 512 macrocells; (2)Industry best 0.18 micron CMOS CPLD: Optimized architecture for effective logic synthesis ; Multi-voltage I/O operation — 1.5V to 3.3V ; (3)Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface; (4)On-The-Fly Reconfiguration (OTF); (5)IEEE1149.1 JTAG Boundary Scan Test; (6)Optional Schmitt trigger input (per pin); (7)Multiple I/O banks on all devices; (8)Unsurpassed low power management DataGATE external signal control; (9)Optional DualEDGE triggered registers; (10)Clock divider (÷ 2,4,6,8,10,12,14,16); CoolCLOCK ; (11)Global signal options with macrocell control; (12)Multiple global clocks with phase selection per macrocell.