Product Summary

The XC2VP7-6FG456I is a PROM. It can provide an easy-to-use, cost-effective method for storing Spartan-II/Spartan-IIE device configuration bitstreams. When the Spartan device is in Master Serial mode, the XC2VP7-6FG456I generates a configuration clock that drives the Spartan PROM. A short access time after the rising clock edge, data appears on the PROM DATA output pin that is connected to the Spartan device DIN pin. The XC2VP7-6FG456I generates the appropriate number of clock pulses to complete the configuration. Once configured, it disables the PROM. When a Spartan device is in Slave Serial mode, the XC2VP7-5FG456C must both be clocked by an incoming signal.

Parametrics

XC2VP7-6FG456I absolute maximum ratings: (1)VCC, Supply voltage relative to GND: –0.5 to +4.0 V; (2)VIN, Input voltage with respect to GND: –0.5 to VCC +0.5 V; (3)VTS, Voltage applied to High-Z output: –0.5 to VCC +0.5 V; (4)TSTG, Storage temperature (ambient): –65 to +150 ℃.

Features

XC2VP7-6FG456I features: (1)Configuration one-time programmable (OTP) read-only memory designed to store configuration bitstreams for Spartan II/Spartan-IIE FPGA devices; (2)Simple interface to the Spartan device; (3)Programmable reset polarity (active High or active Low); (4)Low-power CMOS floating gate process; (5)3.3V PROM; (6)Available in compact plastic 8-pin DIP, 8-pin VOIC, 20-pin SOIC, or 44-pin VQFP packages; (7)Programming support by leading programmer manufacturers; (8)Design support using the Xilinx Alliance and Foundation?series software packages; (9)Guaranteed 20-year life data retention; (10)Pb-free (RoHS-compliant) packaging available.

Diagrams

XC2VP7-6FG456I diagram

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