EPM7064STC100-7N

Programmable Logic Device, QFP100, High-performance, 5.0-V in-system programmability, -25 to 25 mA

Rated 5 Rating 5 | reviews | Write a review

Price:: US $3.33~3.70 / piece [Get Latest Price]

Reference price:

Qty (lots)	Price/lot
	US $3.33~3.70

PartNumber:: EPM7064STC100-7N

Brand:: Altera Corporation - ALTR | Pack: QFP | D/C: 07+

Availability:: Supply Ability: 10000/Week Can Ship Immediately
Delivery: 10-15 Business Days (ships out within 3 Business days)

Quantity:: piece

Total Price:: US $0

Place Order via Escrow Service

Sold By

Ms. Lisa's store

(China (Mainland))

add to my favourite

100% Positive feedback

Detailed seller ratings

Visit Store

Contact Now

Esrcow Service

Place orders confidently and securely via it

Safe payments
Quick and easy transactions
Free service charges

Learn More >>

Previous Next

Products Upload time: 2011-12-16

From Other Seller

Part Number:EPM7064STC100-7N
US $3.33 - 3.70
ECA1HHG4R7

US $10.00 - 10.00 / Piece
(0) Remove
YL-G709

US $65.00 - 68.00 / Piece
(0) Remove
Quantity:

piece

Product Summary

The EPM7064STC100-7N is a high-density, high-performance PLD. It is based on Altera second-generation MAX architecture. Fabricated with advanced CMOS technology, the EEPROM-based EPM7064STC100-7N provides 600 to 5,000 usable gates, ISP, pin-to-pin delays as fast as 5 ns, and counter speeds of up to 175.4MHz. The EPM7064STC100-7N has several enhanced features: additional global clocking, additional output enable controls, enhanced interconnect resources, fast input registers, and a programmable slew rate.

Parametrics

EPM7064STC100-7N absolute maximum ratings: (1)VCC Supply voltage With respect to ground: -2.0 to 7.0 V; (2)VI DC input voltage: -2.0 to 7.0 V; (3)IOUT DC output current, per pin: -25 to 25 mA; (4)TSTG Storage temperature No bias: -65 to 150 ℃; (5)TAMB Ambient temperature Under bias: -65 to 135 ℃; (6)TJ Junction temperature Ceramic packages, under bias: 150 ℃; (7)PQFP and RQFP packages, under bias: 135 ℃.

Features

EPM7064STC100-7N features: (1)High-performance, EEPROM-based programmable logic devices (PLDs) based on second-generation MAXR architecture; (2)5.0-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface available in MAX 7000S devices- ISP circuitry compatible with IEEE Std. 1532; (3)Includes 5.0-V MAX 7000 devices and 5.0-V ISP-based MAX 7000S devices; (4)Built-in JTAG boundary-scan test (BST) circuitry in MAX 7000S devices with 128 or more macrocells; (5)Complete EPLD family with logic densities ranging from 600 to 5,000 usable gates (see Tables 1 and 2); (6)5-ns pin-to-pin logic delays with up to 175.4-MHz counter; (7)frequencies (including interconnect); (8)PCI-compliant devices available.