EPM9320LC84-15

Product Summary

The EPM9320LC84-15 is an in-system-programmable, high-density, high performance EPLD which is based on Altera’s third-generation MAX architecture. Fabricated on an advanced CMOS technology, the EEPROM-based EPM9320LC84-15 provides 6,000 to 12,000 usable gates, pin-to-pin delays as fast as 10 ns, and counter speeds of up to 144 MHz. The -10 speed grade of the EPM9320LC84-15 is compliant with the PCI Local Bus Specification, Revision 2.2. Table 3 shows the speed grades available for EPM9320LC84-15.

Parametrics

EPM9320LC84-15 Absolute maximum ratings:(1)Usable gates: 6,000; (2)Flipflops: 484; (3)Macrocells: 320; (4)Logic array blocks: (LABs) 20; (5)Maximum user I/O pins: 168; (6)tPD1 (ns): 10; (7)tFSU (ns): 3.0; (8)tFCO (ns): 4.5; (9)fCNT (MHz): 144.

Features

EPM9320LC84-15 Features:(1)High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX) architecture; (2)5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Test Action Group (JTAG) interface; (3)Built-in JTAG boundary-scan test (BST) circuitry compliant with IEEE Std. 1149.1-1990; (4)High-density erasable programmable logic device (EPLD) family ranging from 6,000 to 12,000 usable gates (see Table 1); (5)10-ns pin-to-pin logic delays with counter frequencies of up to 144 MHz; (6)Fully compliant with the peripheral component interconnect Special Interest Group’s (PCI SIG) PCI Local Bus Specification, Revision 2.2; (7)Dual-output macrocell for independent use of combinatorial and registered logic; (8)FastTrack Interconnect for fast, predictable interconnect delays; (9)Input/output registers with clear and clock enable on all I/O pins; (10)Programmable output slew-rate control to reduce switching noise; (11)MultiVolt I/O interface operation, allowing devices to interface with 3.3-V and 5.0-V devices; (12)Configurable expander product-term distribution allowing up to 32 product terms per macrocell; (13)Programmable power-saving mode for more than 50% power reduction in each macrocell.

Diagrams