(China (Mainland))
Product Summary
The KFG1216U2A-DIB5 is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. The KFG1216U2A-DIB5 includes control logic, a NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and 4KB for data buffering (DataRAM), split between 2 independent buffers. It has a x16 Host Interface and a random access time speed of 76ns. The KFG1216U2A-DIB5 operates up to a maximum host-driven clock frequency of 54MHz for synchronous reads at Vcc(or Vccq. Refer to chapter 4.2) with minimum 4-clock latency. Below 40MHz it is accessible with minimum 3-clock latency. Appropriate wait cycles are determined by programmable read latency.
Parametrics
KFG1216U2A-DIB5 absolute maximum ratings: (1)Voltage on any pin relative to VSS:-0.5V to +2.45V; (2)Temperature Under Bias:-30 to +125℃; (3)Storage Temperature:-65 to +150℃; (4)Short Circuit Output Current: 5mA; (5)Recommended Operating Temperature:-40 to +85℃.
Features
KFG1216U2A-DIB5 features: (1)Design Technology: 90nm; (2)Supply Voltage: 3.3V (2.7 to 3.6V); (3)Host Interface: 16 bit; (4)5KB Internal BufferRAM: 1KB BootRAM, 4KB DataRAM; (5)SLC NAND Array: (2K+64)B Page Size, (128K+4K)B Block Size; (6)Programmable Burst Read Latency:Latency 3(up to 40MHz), 4, 5, 6, and 7; (7)Multiple Sector Read:Up to 4 sectors using Sector Count Register; (8)Multiple Reset Modes:Cold/Warm/Hot/NAND Flash Resets; (9)Multi Block Erase:up to 64 blocks; (10)Voltage detector generating internal reset signal from Vcc; (11)Hardware reset input (/RP); (12)User-controlled One Time Programmable(OTP) area; (13)Internal 2bit EDC / 1bit ECC; (14)Internal Bootloader supports Booting Solution in system.
Diagrams
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 KFG1216U2M |
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KFG1G16D2M-DEB5 |
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KFG1G16Q2M-DEB5 |
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KFG1G16Q2M-DEB6 |
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