Product Summary

The MT47H16M16BG-37E:B is a SDRAM. The MT47H16M16BG-37E:B uses a double data rate architecture to achieve high-speed operation. The double data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. A single read or write access for the MT47H16M16BG-37E:B effectively consists of a single 4n-bit-wide, oneclock-cycle data transfer at the internal DRAM core and four corresponding n-bit-wide, one-half-clock-cycle data transfers at the I/O balls.

Parametrics

MT47H16M16BG-37E:B absolute maximum ratings: (1)VDD supply voltage relative to VSS, VDD: –1.0 to 2.3 V; (2)VDDQ supply voltage relative to VSSQ, VDDQ: –0.5 to 2.3 V; (3)VDDL supply voltage relative to VSSL, VDDL: –0.5 to 2.3 V; (4)Voltage on any ball relative to VSS, VIN, VOUT: –0.5 to 2.3 V; (5)Input leakage current; any input 0V ≤ VIN ≤ VDD; all other balls not under test = 0V, II: –5 to 5 μA; (6)Output leakage current; 0V ≤ VOUT ≤ VDDQ; DQ and ODT disabled, IOZ: –5 to 5 μA; (7)VREF leakage current; VREF = valid VREF level, IVREF: –2 to 2μA.

Features

MT47H16M16BG-37E:B features: (1)VDD = +1.8V ±0.1V, VDDQ = +1.8V ±0.1V; (2)JEDEC-standard 1.8V I/O (SSTL_18-compatible); (3)Differential data strobe (DQS, DQS#) option; (4)4n-bit prefetch architecture; (5)Duplicate output strobe (RDQS) option for x8; (6)DLL to align DQ and DQS transitions with CK; (7)4 internal banks for concurrent operation; (8)Programmable CAS latency (CL); (9)Posted CAS additive latency (AL); (10)WRITE latency = READ latency - 1 tCK; (11)Selectable burst lengths (BL): 4 or 8; (12)Adjustable data-output drive strength; (13)64ms, 8192-cycle refresh; (14)On-die termination (ODT); (15)Industrial temperature (IT) option; (16)Automotive temperature (AT) option; (17)RoHS-compliant; (18)Supports JEDEC clock jitter specification.

Diagrams

MT47H16M16BG-37E:B Functional Block Diagram

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