(China (Mainland))
Product Summary
The TDA8754HL/27/C1,51 is a triple 8-bit ADC with controllable gain and clamps for the digitizing of large bandwidth R, G, B signals. Clamp level, gain, and all the other settings are controlled via a serial interface (either I2C-bus or 3-wire, selected through a logic input). The gain of the TDA8754HL/27/C1,51 is optimized for stability versus temperature variations. The TDA8754HL/27/C1,51 also includes a PLL that generates the ADC clock which can be locked to the horizontal line frequency. The PLL jitter is minimized for high resolution PC graphics applications. An external clock can also be used to clock the ADC.
Parametrics
TDA8754HL/27/C1,51 specifications: (1)VCCA analog supply voltage for R, G, B channels: 4.75 to 5.25 V; (2)VDD logic supply voltage for I2C-bus and 3-wire interface: 3.0 to 5.25 V; (3)VCCD digital supply voltage: 4.75 to 5.25 V; (4)VCC(O) output stages supply voltage for R, G, B channels: 3.0 to 3.6 V; (5)VCCA(PLL) analog PLL supply voltage: 4.75 to 5.25 V; (6)VCC(O)(PLL) output PLL supply voltage: 4.75 to 5.25 V.
Features
TDA8754HL/27/C1,51 features: (1)Triple 8-bit Analog-to-Digital Converter (ADC); (2)Sampling rate up to 170 MHz; (3)IC controllable via a serial interface, which can be either I2C-bus or 3-wire, selected via a TTL input pin; (4)IC analog input 0.5 to 1.1 V (peak-to-peak value) to have full-scale ADC input; (5)Clamps for programming a clamp level through a clamping code between -63 and +64 by steps of 1 LSB; (6)Controllable gain stages: gain controlled independently on the 3 channels via the serial interface to have a full-scale resolution to 1%; (7)Low gain variation at different temperatures; (8)Analog bandwidth of 400 MHz; (9)Controllable PLL via the serial interface generates the ADC clock. It can be locked on line frequencies from 15 kHz up to 280 kHz; (10)Integrated PLL divider.
Diagrams
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 TDA8754HL/27/C1,51 |
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