TMS320C6416TGLZ

Product Summary

The TMS320C6416TGLZ is a fixed-point digital signal processor. It is based on the second-generation high performance, advanced VelociTI very-long-instruction-word (VLIW) architecture (VelociTI.2) developed by Texas Instruments (TI), making the DSP an excellent choice for wireless infrastructure applications. The TMS320C6416TGLZ has two high-performance embedded coprocessors [Viterbi Decoder Coprocessor (VCP)and Turbo Decoder Coprocessor (TCP)] that significantly speed up channel-decoding operations on-chip. The VCP operating at CPU clock divided-by-4 can decode over 833 7.95-Kbps adaptive multi-rate (AMR) [K = 9, R = 1/3] voice channels. The TMS320C6416TGLZ has a complete set of development tools which includes: an advanced C compiler with C64x-specific enhancements, an assembly optimizer to simplify programming and scheduling, and a Windows debugger interface for visibility into source code execution.

Parametrics

TMS320C6416TGLZ absolute maximum ratings: (1)Supply voltage ranges: CVDD:-0.5V to 1.5V, DVDD:-0.5V to 4.4V; (2)Input voltage ranges: (except PCI), VI:-0.5V to 4.4V, (PCI), VIP:-0.5V to DVDD+0.5V; (3)Output voltage ranges: (except PCI), VO:-0.5V to 4.4V, (PCI), VOP:-0.5V to DVDD+0.5V; (4)Operating case temperature ranges, TC: (default and M version) 0℃ to 90℃; (5)Storage temperature range, Tstg:-65℃ to 150℃.

Features

TMS320C6416TGLZ features: (1)1.67-/1.39-/1.17-/1-ns Instruction Cycle; (2)600-/720-/850-MHz, 1-GHz Clock Rate; (3)Eight 32-Bit Instructions/Cycle; (4)Twenty-Eight Operations/Cycle; (5)4800, 5760, 6800, 8000 MIPS; (6)Fully Software-Compatible With C62x; (7)C6414/15/16 Devices Pin-Compatible; (8)Extended Temperature Devices Available; (9)Non-Aligned Load-Store Architecture; (10)64 32-Bit General-Purpose Registers; (11)Instruction Packing Reduces Code Size; (12)All Instructions Conditional; (13)Byte-Addressable (8-/16-/32-/64-Bit Data); (14)8-Bit Overflow Protection; (15)Bit-Field Extract, Set, Clear; (16)Normalization, Saturation, Bit-Counting; (17)VelociTI.2 Increased Orthogonality; (18)Supports Over 833 7.95-Kbps AMR; (19)Programmable Code Parameters; (20)Supports up to 10 2-Mbps or 60 384-Kbps 3GPP (6 Iterations); (21)Programmable Turbo Code and Decoding Parameters; (22)One 64-Bit (EMIFA), One 16-Bit (EMIFB); (23)Glueless Interface to Asynchronous Memories (SRAM and EPROM) and Synchronous Memories (SDRAM, SBSRAM, ZBT SRAM, and FIFO); (24)1280M-Byte Total Addressable External Memory Space.

Diagrams