XC2C512-10FTG256C

Product Summary

The XC2C512-10FTG256C is a 512-macrocell device. The XC2C512-10FTG256C is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved. The XC2C512-10FTG256C consists of thirty two Function Blocks inter-con-nected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks of the XC2C512-10FTG256C consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation.

Parametrics

XC2C512-10FTG256C absolute maximum ratings: (1)VCC, Supply voltage relative to ground: –0.5 to 2.0 V; (2)VCCIO, Supply voltage for output drivers: –0.5 to 4.0 V; (3)VJTAG,JTAG input voltage limits: -0.5 to 4.0 V; (4)VCCAUX, JTAG input supply voltage: -0.5 to 4.0 V; (5)VIN,Input voltage relative to ground: –0.5 to 4.0 V; (6)VTS,Voltage applied to 3-state output:–0.5 to 4.0 V; (7)TSTG,Storage Temperature (ambient): –65 to +150℃; (8)TJ, Junction Temperature: +150℃.

Features

XC2C512-10FTG256C features: (1)Optimized for 1.8V systems: As fast as 7.1 ns pin-to-pin delays; As low as 14 μA quiescent current; (2)Industry’s best 0.18 micron CMOS CPLD: Optimized architecture for effective logic synthesis; Multi-voltage I/O operation — 1.5V to 3.3V; (3)Available in multiple package options: 208-pin PQFP with 173 user I/O; 256-ball FT (1.0mm) BGA with 212 user I/O; 324-ball FG (1.0mm) BGA with 270 user I/O; Pb-free available for all packages; (4)Advanced system features: Fastest in system programming; (5)1.8V ISP using IEEE 1532 (JTAG) interface: IEEE1149.1 JTAG Boundary Scan Test; Optional Schmitt-trigger input (per pin); Unsurpassed low power management; (6)DataGATE enable signal control: Four separate I/O banks; RealDigital 100% CMOS product term generation; Flexible clocking modes; (7)Optional DualEDGE triggered registers; (8)Clock divider (divide by 2,4,6,8,10,12,14,16); (9)CoolCLOCK.

Diagrams