ZL30105

Product Summary

The ZL30105 is a T1/E1/SDH Stratum 3 Redundant System Clock Synchronizer for AdvancedTCA and H.110. It contains a digital phase-locked loop (DPLL), which provides timing and synchronization for SDH and T1/E1 transmission equipment. The ZL30105 provides advanced support for systems deploying redundant clocks. The applications of the ZL30105 include Synchronization and timing control for multi-trunk SDH and T1/E1 systems such as DSLAMs, Gateways and PBXs and Clock and frame pulse source for AdvancedTCA- and other time division multiplex (TDM) buses.

Parametrics

ZL30105 absolute maximum ratings: (1)Supply voltage VDD_R: -0.5 to 4.6 V; (2)Core supply voltage, VCORE_R; -0.5 to 2.5 V; (3)Voltage on any digital pin, VPIN: -0.5 to 6 V; (4)Voltage on OSCi and OSCo pin, VOSC: -0.3 to VDD + 0.3 V; (5)Current on any pin IPIN: 30 mA; (6)Storage temperature, TST: -55 to 125℃; (7)TQFP 64 pin package power dissipation, PPD: 500 mW; (8)8ESD rating, VESD: 2kV.

Features

ZL30105 features: (1)Synchronizes to clock-and-sync-pair to maintain minimal phase skew between the master-clock and the redundant slave-clock; (2)Supports ITU-T G.813 option 1, G.823 for 2048 kbit/s and G.824 for 1544 kbit/s interfaces; (3)Supports Telcordia GR-1244-CORE Stratum 3/4/4E; (4)Supports ANSI T1.403 and ETSI ETS 300 011 for ISDN primary rate interfaces; (5)Accepts three input references and synchronizes to any combination of 2 kHz, 8 kHz, 1.544 MHz, 2.048 MHz, 8.192 MHz, 16.384 MHz or 19.44 MHz inputs; (6)Provides a range of clock outputs: 1.544 MHz (DS1), 2.048 MHz (E1), 3.088 MHz, 16.384 MHz, and 19.44 MHz (SDH), and either 4.096 MHz and 8.192 MHz or 32.768 MHz and 65.536 MHz, and a choice of 6.312 MHz (DS2), 8.448 MHz (E2), 44.736 MHz (DS3) or 34.368 MHz (E3); (7)Provides 5 styles of 8 kHz framing pulses and a 2 kHz multi-frame pulse; (8)Holdover frequency accuracy of 1x10-8; (9)Selectable loop filter 1.8 Hz, 3.6 Hz or 922 Hz; (10)Less than 24 psrms intrinsic jitter on the 19.44 MHz output clock, compliant with GR-253-CORE OC-3 and G.813 STM-1 specifications; (11)Less than 0.6 nspp intrinsic jitter on all output clocks and frame pulses; (12)Manual or Automatic hitless reference switching between any combination of valid input reference frequencies; (13)Provides Lock, Holdover and selectable Out of Range indication; (14)Simple hardware control interface; (15)Selectable external master clock source: Clock Oscillator or Crystal.

Diagrams