(China (Mainland))
Product Summary
The HY5DU561622DT-D43 is a 268,435,456-bit CMOS Double Data Rate(DDR) Synchronous DRAM. It is ideally suited for the point-to-point applications which requires high bandwidth. The HY5DU561622DT-D43 offers fully synchronous operations referenced to both rising and falling edges of the clock. While all addresses and control inputs are latched on the rising edges of the CK (falling edges of the /CK), Data, Data strobes and Write data masks inputs are sampled on both rising and falling edges of it.
Parametrics
HY5DU561622DT-D43 absolute maximum ratings: (1)Operating Temperature (Ambient) TA: 0 ~ 70 ℃; (2)Storage Temperature TSTG: -55 ~ 150 ℃; (3)Voltage on VDD relative to VSS VDD: -1.0 ~ 3.6 V; (4)Voltage on VDDQ relative to VSS VDDQ: -1.0 ~ 3.6 V; (5)Voltage on inputs relative to VSS VINPUT: -1.0 ~ 3.6 V; (6)Voltage on I/O pins relative to VSS VIO: -0.5 ~3.6 V; (7)Output Short Circuit Current IOS: 50 mA; (8)Soldering Temperature . Time TSOLDER: 260 10 ℃ Sec.
Features
HY5DU561622DT-D43 features: (1)All inputs and outputs are compatible with SSTL_2 interface; (2)Fully differential clock inputs (CK, /CK) operation; (3)Double data rate interface; (4)Source synchronous - data transaction aligned to bidirectional data strobe (DQS); (5)x16 device has 2 bytewide data strobes (LDQS, UDQS) per each x8 I/O; (6)Data outputs on DQS edges when read (edged DQ) ; (7)Programmable CAS latency 2 / 2.5 supported; (8)Programmable Burst Length 2 / 4 / 8 with both sequential and interleave mode; (9)Internal 4 bank operations with single pulsed /RAS; (10)tRAS Lock-Out function supported.
Diagrams
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