XC2S30-5VQG100C

Field-Programmable Gate Array, XC2S30-5VQG100C, 2.5V, 100-VQFP

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PartNumber:: XC2S30-5VQG100C

Brand:: Xilinx, Inc - Xilinx | Pack: QFP | D/C: 10+

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Products Upload time: 2012-06-11

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Product Summary

The XC2S30-5VQG100C is an Field-Programmable Gate Array. It offers densities ranging from 15,000 to 200,000 system gates. System performance is supported up to 200 MHz. Features of the XC2S30-5VQG100C include block RAM (to 56K bits), distributed RAM (to 75,264 bits), 16 selectable I/O standards, and four DLLs. Fast, predictable interconnect means that successive design iterations continue to meet timing requirements. The XC2S30-5VQG100C is a superior alternative to mask-programmed ASICs.

Parametrics

XC2S30-5VQG100C absolute maximum ratings: (1)VCCINT Supply voltage relative to GND: –0.5 to 3.0 V; (2)VCCO Supply voltage relative to GND: –0.5 to 4.0 V; (3)VREF Input reference voltage: –0.5 to 3.6 V; (4)VIN Input voltage relative to GND 5V tolerant I/O: –0.5 to 5.5 V, No 5V tolerance: –0.5 to VCCO+0.5 V; (5)VTS Voltage applied to 3-state output 5V tolerant I/O: –0.5 to 5.5 V, No 5V tolerance: –0.5 to VCCO+0.5 V; (6)TSTG Storage temperature (ambient): –65 to +150 ℃; (7)TJ Junction temperature: - +125 ℃.

Features

XC2S30-5VQG100C features: (1)SelectRAM hierarchical memory: 16 bits/LUT distributed RAM, Configurable 4K bit block RAM, Fast interfaces to external RAM; (2)Fully PCI compliant; (3)Low-power segmented routing architecture; (4)Full readback ability for verification/observability; (5)Dedicated carry logic for high-speed arithmetic; (6)Efficient multiplier support; (7)Cascade chain for wide-input functions; (8)Abundant registers/latches with enable, set, reset; (9)Four dedicated DLLs for advanced clock control; (10)Four primary low-skew global clock distribution nets; (11)IEEE 1149.1 compatible boundary scan logic.