XC5VLX155-1FFG1153

Product Summary

The XC5VLX155-1FFG1153 is an FPGA. It contains five distinct platforms (sub-families), the most choice offered by any FPGA family. Each platform contains a different ratio of features to address the needs of a wide variety of advanced logic designs. Built on a 65-nm state-of-the-art copper process technology, the XC5VLX155-1FFG1153 is a programmable alternative to custom ASIC technology. The XC5VLX155-1FFG1153 offers the best solution for addressing the needs of high-performance logic designers, high-performance DSP designers, and high-performance embedded systems designers with unprecedented logic, DSP, hard/soft microprocessor, and connectivity capabilities.

Parametrics

XC5VLX155-1FFG1153 absolute maximum ratings: (1)Internal supply voltage relative to GND:–0.5 to 1.1 V; (2)Auxiliary supply voltage relative to GND:–0.5 to 3.0 V; (3)Output drivers supply voltage relative to GND:–0.5 to 3.75 V; (4)Key memory battery backup supply:–0.5 to 4.05 V; (5)Input reference voltage:–0.5 to 3.75 V; (6)3.3V I/O input voltage relative to GND(user and dedicated I/Os):–0.75 to 4.05 V; (7)3.3V I/O input voltage relative to GND (restricted to maximum of 100 user I/Os):–0.95 to 4.4V(Commercial Temperature), –0.85 to 4.3V(Industrial Temperature); (8)2.5V or below I/O input voltage relative to GND (user and dedicated I/Os):–0.75 to VCCO + 0.5 V; (9)Current applied to an I/O pin, powered or unpowered:±100 mA; (10)Total current applied to all I/O pins, powered or unpowered: 100 mA; (11)Voltage applied to 3-state 3.3V output (user and dedicated I/Os): –0.75 to 4.05 V; (12)Voltage applied to 3-state 2.5V or below output (user and dedicated I/Os):–0.75 to VCCO + 0.5 V; (13)Storage temperature (ambient):–65 to 150℃; (14)Maximum soldering temperature:+220℃; (15)Maximum junction temperature:+125℃.

Features

XC5VLX155-1FFG1153 features: (1)Real 6-input look-up table (LUT) technology; (2)Dual 5-LUT option; (3)Improved reduced-hop routing; (4)64-bit distributed RAM option; (5)SRL32/Dual SRL16 option; (6)Digital Clock Manager (DCM) blocks for zero delay buffering, frequency synthesis, and clock phase shifting; (7)PLL blocks for input jitter filtering, zero delay buffering, frequency synthesis, and phase-matched clock division; (8)True dual-port RAM blocks; (9)Enhanced optional programmable FIFO logic; (10)Built-in optional error-correction circuitry; (11)Optionally program each block as two independent 18-Kbit blocks; (12)1.2 to 3.3V I/O Operation; (13)Source-synchronous interfacing using ChipSync technology; (14)Digitally-controlled impedance (DCI) active termination; (15)Flexible fine-grained I/O banking; (16)High-speed memory interface support; (17)25 x 18, two’s complement, multiplication; (18)Optional adder, subtracter, and accumulator; (19)Optional pipelining; (20)Optional bitwise logical functionality; (21)Dedicated cascade connections; (22)SPI and Parallel FLASH interface; (23)Multi-bitstream support with dedicated fallback reconfiguration logic; (24)Auto bus width detection capability; (25)On-chip/Off-chip thermal monitoring; (26)On-chip/Off-chip power supply monitoring; (27)JTAG access to all monitored quantities.

Diagrams